Low Voltage Tunneling in Ultra-Thin Oxides: A Monitor for Interface States and Degradation

Sub-0.1microns technologies require gate oxide thicknesses t sub (ox) 10 sup (18) cm sup (-3). The heavily doped substrate leads to the presence of a thermionic barrier that opposes the direct tunneling (DT) of gate electrons when the applied gate voltage is in the range - |V sub (FB)|