Modeling of direct tunneling and surface roughness effects on C-V characteristics of ultra-thin gate MOS capacitors

Effects of direct tunneling and surface roughness on the capacitance-voltage characteristics of ultra-thin gate deep submicron MOS transistors have been studied. An improved equivalent circuit model to account for surface roughness and direct tunneling on the ultra-thin gate MOS capacitors in a unified manner is proposed. The capacitance subject to direct tunneling and surface roughness effect is smaller than that without surface roughness effect. (C) 2001 Elsevier Science Ltd. All rights reserved.