Modeling of Mismatch Effect in Submicron MOSFETs Based on BSIM3 Model and Parametric Tests

Mismatch between identically designed MOS transistors plays an important role in the performance of analog circuits. This paper reports on an MOS transistor mismatch model applicable for submicron CMOS technology and developed based on the industry standard BSIM3v3 model. Despite the high complexity of hte BSIM3 model, a simple and unified expression was derived to formulate the effect of MOSFET mismatch. A quick way to estimate drain current mismatch based on parametric test data was also suggested.