Monolithically integrated enhancement mode InP MISFET inverter.
01 January 1986
Three InP MISFET's have been monolithically integrated on an Fe-doped semi-insulating InP substrate in conjunction with three integrated load resistors forming an inverter. The epitaxial layers have been grown by chloride vapor phase epitaxy. The MISFET's exhibit transconductances as high as 200 mS/mm for a gate length of 1micron. The circuit consists of one MISFET that is operated as a one transistor-inverter stage in isolation and a two-stage inverter whose output is connected to the gate of an FET. For two-stage inverters we have obtained typical high and low level noise margins of 0.4 and 0.3 volt at a bias level of 1.5 volts.