Photonic I/O's at The PWB & Chip Levels?

For future VLSI-based systems, inter-chip interconnection problems will become increasingly severe. The key I/O problems are: 1) The growing number of I/O pins on chips, 2) I/O speed, power, and current surge limitations, 3) the difficulty of maintaining signal integrity of fast and small signals, and synchronization between parallel data and control signals, and 4) ESD (Electro-Static Discharge)/EOS (Electrical Over-Stress) damage and ESD induced EMI protection.