Predicting Performance Penalty for Fault Tolerance in Roving STARs

The maximum clock rate of a sequential circuit and the minimum propagation delay through a combinational circuit are both functions of the propagation delay of signals traveling through a circuit's critical path(s). Once a circuit or application is completely mapped (after placement and routing are complete) to an FPGA the maximum operating speed of the application can be accurately determined. Reconfiguring a circuit's placement for fault tolerance of other applications often increases the propagation delay through the critical path(s). To help guide fault tolerant (FT) reconfiguration of circuit placement, it is advantageous to accurately predict the performance penalty of the reconfiguration before the placement is incrementally routed. In this paper we present procedures for estimating the minimum and maximum performance penalty of changing the physical placement of logic cell functions in a circuit's critical paths(s) for FT reconfiguration. Our methods predict the performance penalty before the circuit is incrementally routed; therefore, they can be used to guide FT incremental placement. Our procedures are based on a FPGA model with different lengths of wiring segments available for routing and on predicting the programmable resources a router will use to route elements in a circuit's critical path. We have applied our method to an actual FT adaptive computing system and tested it using benchmark circuits. In this paper we also present the idea of adjusting clock frequency for fault tolerance. After adjusting circuit placements and routing for fault tolerance, we use post place and route timing analysis to adjust the system clock frequency. This allows system performance to degrade gradually in the presence of faults.