Predictive Analysis of Sensitivity to Chip-Routing Parasitics

Key unknows in the early stages of design of high-performance analog integrated circuits are the loading effects and potential for noise injection of the implementation of the interconnections on the chip. The layout variables are length of interconnects, choice of interconnect material, width of runners, and the adjacencies. The effect on performance of these unknowns can be particularly significant for a chip which operates at high speed or low signal levels. Experienced designers understand and anticipate potential problem areas in their designs, and take appropriate steps to avoid, for example, long interconnects.