Problems Using Boundary-Scan for Memory Cluster Tests

Boundary-scan testing is used to overcome many of the testability issues facing today's higher density designs. In the past, boundary-scan has been used successfully to perform interconnect testing between boundary-scan supporting devices. There has been an increased use of testing clusters of non-boundary-scan devices that are surrounded by boundary-scan access at the edge of the circuit both in manufacturing and system test. Boundary-scan is also being used to perform cluster testing of memory devices that do not support boundary-scan directly. These specialized boundary-scan tests are written to emulate a functional test pattern flow which requires a relatively precise control of the timing constraints in a synchronous clock window for Synchronous Dynamic Random Access Memory (SDRAM). New interface architectures are also stressing the timing constraints available from a boundary-scan based test. This paper discusses the issues impeding boundary-scan based memory testing and suggests some alternative methods for testing these memory devices when boundary-scan testing is unattainable. (This paper is a formal presentation of the information presented at the Board Test Workshop 2006 that has previously been approved for release in 2006. It is being formalized as a reference document for the iNEMI boundary-scan adoption project which has identified memory testing as the number one boundary-scan issue facing test engineering today.)