Process Control of Threshold Voltage in the GaAs ERGIC Process.

Determining the threshold voltage of an EFET is one of the most critical steps in the GaAs Epitaxial Recessed Gate Integrated Circuit (ERGIC) process. The threshold voltage (V sub t) is established by iteratively etching the channel with a wet chemical etch, then measuring the source-drain current (I sub etch) at 2 volts, until the current reaches a predetermined value. This work examines the process variables which, in the past, have lead to a poor correlation between I sub etch and V sub t. The results of these experiments indicate that GaAs FETs can be fabricated with threshold voltages that strongly correlate with etch currents.