Processing enhanced SEU tolerance in high density SRAMs.

We report theoretical calculations and experimental verification of an increase in memory SEU tolerance when Sandia's 2micron- technology 16K SRAMs are fabricated with ATT-BL's 1micron process. An advanced 2D transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes resulting from such processing differences. Error cross-section data, performed at the Berkeley cyclotron, on the first such device lot indicate that total improvement in threshold LET is a factor of 2 or better. A saturation phenomenon associated with high LET events will be described and physical mechanisms responsible for the saturation will be discussed.