Progress Toward a 30 nm Silicon MOS Gate Technology

We report on progress toward scaling both NMOS and PMOS transistors to a gate length of 30nm. We describe lithography and pattern transfer results suitable to meet this goal. Scanning capacitance microscopy is used to determine the effective channel lengths and source drain junction depths on cross-sectioned devices to optimize the fabrication process. We present interim electrical results obtained for high performance, down to L sub g=57nm, NMOS and PMOS transistors made using this process. We have also used a device simulation program to predict sub-threshold current for the NMOS transistors with gate lengths from 40nm to 26nm. The simulation provides insights into the effects of CD control and edge roughness on leakage current, and has implications for extending large scale integration of MOS technology beyond 50 nm.