Severe Thickness Variation of Sub-3nm Gate Oxide Due to Si Surface Faceting, Poly-Si Intrusion and Corner Stress

In the fabrication of CMOS devices with sub-3nm gate oxide, we have observed severe variation of the oxide thickness (t sub (ox)). For devices with 2.5-nm t sub (ox) at the center of the channel, the physical t sub (ox) ranges from 1.8 nm to 4.2 nm on various positions of the channel. It is caused by different oxide growth rate determined by the orientation and stress conditions of the local Si surface especially at the rounded corners of the shallow-trench isolation (STI). In addition, poly-Si intrusion from the gate electrode also causes local t sub (ox) thinning. Such severe variation of L sub (ox) becomes the challenge of STI engineering, gate-oxide scaling and qualification.