Simulation of npn transistors in the 1.25micron BiCMOS process.

This memorandum discusses the simulation of the isolated npn transistors in AT&T's 1.25micron BiCMOS technology, assuming nominal processing. The sequence starts with process simulation and continues through extraction of extended Gummel-Poon (E G-P) type compact circuit models, which are suitable for use in ADVICE circuit simulation. In doing the npn simulations, a simplified, approximate technique is used which significantly reduces the time and effort required. In this technique, several simple npn geometries are simulated, and an E G-P model is extracted for each. To model any npn transistor in ADVICE, the appropriate combination of these E G-P models is connected together; this combination can be easily determined from the npn device's layout. DC measurements on actual devices show that the simulated results are generally accurate. At high currents, there are some discrepancies between experiment and simulation due to device heating. Measurements were made of the device temperature rise, and it was found that the discrepancies can be explained by this rise.