Sleipnir - An Instruction Level Simulator Generator

Instruction level simulators occupy a central role in software development for embedded processors. They provide a convenient virtual platform for testing, debugging and optimizing code, without the awkwardness of working with a test/evaluation board. However, instruction level simulators are tedious to write. The programmer must make significant tradeoffs between simulation speed, portability (of the simulator), retargetability (changing the simulator target) and maintainability. This paper presents the Sleipnir simulator generator. Sleipnir provides a convenient model for writing instruction level simulators that maximizes portability, retargetability and maintainability while preserving high simulation speeds. The Sleipnir machine description is sufficiently flexible to even allow cycle accurate simulators to be specified. Sleipnir supports a wide variety of architectures. It has been used successfully to generate fast instruction level simulators for the Lucent Technologies DSP1600, Texas Instruments C62xx series DSps, ARM/Thumb, Motorola M*Core, and the integer part of the Mips architecture.