Towards energy-efficient packet processing in access nodes

One of the main building blocks found in Ethernet based access nodes is the packet processor (PP) also called the network processor. The PP is typically implemented on lineboards of access nodes such as Digital Subscriber Line Access Multiplexers (DSLAM's) for copper and Optical Line Terminals (OLT's) for fiber. It mainly deals with L2 functions such as VLAN tagging, forwarding and QoS at the packet level. Other functions which can be implemented in the packet processor are multicast, protocol adaptation functions and L2 security features such as MAC address spoofing. In this paper we give an overview of the different paths towards energy efficient PPs for different traffic mixes. For this purpose we elaborate on a simplified block diagram of the PP and show the relationship between the incoming data and packet rates. After revisiting the dynamic nature of the data usage by the typical broadband consumers, we propose an empirical model relating the energy consumption of the PP versus the packet rate and other design technology parameters. The energy efficiency of the PP when implemented in different technologies reveals the different cost/power tradeoffs. Additionally we will show that potential energy saving can be realized when designing a PP that is optimized for the expected peak load and scales-up with the actual traffic load. Two use cases in the numerical result section, one for copper and one for fiber based access networks, showed that up to 25% energy saving in the PP can be realized.