Towards Massively Parallel Automatic Test Generation

We describe a new automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques. Our approach is radically different from the conventional methods used to generate tests for a circuit from its gate level description. A digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links.