Towards Understanding the Performance of P4 Programmable Hardware

The advent of programmability into data plane devices introduced variability in the packet processing delays, which depends on the pipeline complexity. P4 is a popular language for programming packet processors, which abstracts the processing pipeline of a data plane device using a limited set of constructs. Understanding the impact of different P4 constructs on packet latency can be used to build static models for packet latency based on the P4 programs. In this paper, we first analyze the impact of a basic set of P4 constructs on packet processing latency to derive the influential parameters. Then, we use the derived results to propose a method for estimating the packet latency of P4-based network functions implemented using the surveyed P4 constructs. Finally, we validate the accuracy of the proposed method by applying it to realistic network functions.