Traffic Service Position System No. 1B: Real-Time Architecture Utilizing the DMERT Operating System

The Traffic Service Position System No. IB (TSPS No. IB) realtime architecture was designed to meet the project goals discussed in Ref. 1. The implementation of this architecture entailed four major developments: (t) Replacement of the Stored Program Control No. 1A (SPC 1A) of TSPS No. 1 with the 3B20D Processor, the TSPS Peripheral System Interface (PSI), and microcode to execute the SPC 1A instruction set, 775 which together comprise the Stored Program Control No. IB (SPC IB) (ii) Emulation of most existing TSPS No. 1 software structured as a process under the Duplex Multi-Environment Real-Time (DMERT) operating system (iii) Development of additional processes to support the emulation (iv) Integration of the PSI and TSPS peripheral maintenance into the overall DMERT maintenance structure. Before discussing the TSPS No. IB real-time architecture, this paper presents two sections of background information. Section II presents an overview of how TSPS operates using the SPC 1A. Section III reviews the fundamentals of DMERT, and Section IV describes the SPC IB and the TSPS No. IB software architectures. These sections enable the reader to understand the real-time architecture of the TSPS No. IB. More detailed information can be obtained by reading the references. II. TSPS NO. 1 REAL-TIME ARCHITECTURE