Understanding Clock Skew in Synchronous Systems

This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in designing such fully pipelined architectures. These include clock skew, clock distribution network, buffering, timing simulation, and testing. A total of six bit-level pipelined designs, including a multiplier, and FIR filter block, and a multi-channel multiply-accumulate/add chip, have now been fabricated in CMOS technology. These chips have been tested both for functionality and speed. The results of these tests and the applications of these chips are presented and discussed.