Validating the Functional Correctness of Incomplete Logic Circuits with the Aid of a Verification System

This paper presents an attempt to fill the gap between top- down circuit design and bottom-up circuit verification. We report preliminary result on the functional verification of incomplete logic circuits with the aid of the VeryFun system. [1], which is a rule-based functional verification system. Our approach of dealing with incomplete logic circuits is to allow users to tailor generic definitions provided by the verification system.