Video Clip Engine.

A feasibility study and a prototype design of an image sequence hardware platform is presented. The primary objective of this hardware engine is to provide a programmable high speed simulator for developing video compression algorithms and accessing image sequence quality. In addition to a general purpose image sequence simulator the machine will serve as a hardware prototype system for the design of special VLSI custom chips. The architecture consists of a reconfigurable array of processing elements. Each processing element (board) has four bidirectional 16 bit data busses and one control bus. The processing element itself consists of four DSP32Cs, configured into a linear processing array with tranparant nearest neighbor memory access.