VLSI chip for digital TV compression.

A VLSI chip has been designed and produced to give compression adequate for transmission of television over a 45 Mbit/s channel with quality reproduction. Chips produced on two shuttles have not yielded any total working chips. However, measurements made on partial-working chips show that the function is correct and speed is adequate. A simple predictive coding algorithm is incorporated in the chip. The major portion of the compression or reconstruction circuit is implemented in one VLSI chip using 2.5 micron design rules. Compression is accomplished using this chip with two small ROM chips. Reconstruction is done with the same VLSI chip and one ROM chip. Some details of the circuit are presented along with results of testing the chip. The MULGA CAD system was revised to produce a layout for 1. 75 micron design rules and the data sent to Department 52156 for their use in generating a production chip.