VLSI Implementations of Neural Network Models.

Three experimental CMOS VLSI circuits implementing connectionist neural network models are discussed in this paper. These chips contain networks of highly interconnected simple processing elements that execute a task distributed over the whole network. A combination of analog and digital computation allows us to build compact circuits so that large networks can be packed on a single chip. Such networks are well-suited for pattern matching and classification tasks, operations that are held to solve efficiently on serial architectures.