Integrated Circuits for Channel Coding in 3G Cellular Mobile Wireless Systems

This article considers the 3G decoder design problem and, using case-studies, describes two 3G decoder solutions using application specific integrated circuits (ASICs). The first device is targeted for basestation deployment and is based on a unified architecture for convolutional and turbo decoding. The second device is a dedicated high-speed radix-4 logMAP turbo decoder targeted for user equipment (UE) which is motivated by the requirements for high speed downlink packet access (HSDPA). Both devices have been fabricated to 0.18 mum CMOS technology, and whilst optimized for either basestation or UE may be used in both applications.