Multi-scale modeling of thin film deposition: applications to silicon device processing

Metallization is the 'back-end' of the integrated circuit (IC) fabrication process where the transistor interconnections are formed. Fig. 1 shows this part of a static random access memory chip. Metal lines for electrical connections (Al and Cu) in Si devices are deposited as blanket films, and etched or polished back to define the conducting lines. The deposition of insulating layers of materials such as SiO sub 2 complete each vertical level of metallization. Barrier layer films are deposited on the insulating layer to prevent the conducting metal from diffusing into or reacting with the insulating layers, and ultimately to protect the electrically active Si regions.