Optimized ASIC/FPGA design flow for energy efficient network node

Abstract: This article describes the ENERSAVE research project, which is funded by the German ministry of research, whose target is to gain a 30% power reduction for network nodes via introduction of a holistic, energy aware design flow for ASIC and FPGA design. Using today's state of the art design methods, advanced calculation of system power budgets is a major challenge as current methods do not offer sufficient means for supporting energy awareness and efficiency throughout the complete component design process. The ENERSAVE project is developing a methodology to support power awareness and provides the ability to target power constraints from the system level all the way down to the silicon. It introduces formal tools for power optimizations and demonstrates, on an optical transmission system card, how usage of this new design methodology enables the envisioned power target to be achieved. This article presents methodology improvement results to date, and offers a preview of expected demonstrable results at the end of the project in 2014.