Path Delay Fault Simulation of Sequential Circuits

A differential algorithm for concurrent simulation of path delay faults in sequential circuits is presented. The simulator analyzes all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output, for vector-pairs and considers the hazard states occurring between vectors. The main contribution is in methods of propagating signals between time-frames. An optimistic method assumes that all non-destination flip-flops are not affected by delays. The pessimistic method converts all non-destination flip-flops with non-steady values to the unknown state before these values are propagated beyond the time-frame in which a path is activated. A 13-valued algebra is shown to improve the efficiency of fault simulation. IndexTerms-delay test, fault models, fault simulation, path delay faults, sequential circuit timing analysis.