Quater-Imaginary for Complex Arithmetic Circuits

Arithmetic operations involving complex numbers are widely used in the signal processing functions of the physical layer of modern wireless and wireline communication systems, electronic instrumentation and control systems. With the ever increasing throughput requirements of the communication standards, the power consumption of the hardware realization is going beyond the budget. Arithmetic circuits based on binary numeral system that have been optimized rigorously over the past decades are currently being used for the computation involving complex numbers. In this paper, we present the potential of arithmetic circuits based on the Quater-imaginary (QI) base numeral system to reduce power consumption. We show that for a multiplier circuit implementation in the QI base, the savings in power and area consumption could be up to 40% when synthesized in 28nm TSMC standard cell technology node.