Real-time Implementation of a 4.4 Gbit/s QPSK Intradyne Receiver Using a Field Programmable Gate Array (FPGA)
23 November 2006
We report on the real-time implementation of a QPSK intradyne receiver at a data rate of 4.4 GBit/s. Both, block phase estimation and differential detection were successfully demonstrated with bit error ratios well below the threshold of modern forward- error correction codes.
