Recirculating Ultrasonic Stores: An Economical Approach To Sequential Storage with Bit Rates Beyond 100 MHz

In a computer of conventional organization, a central processor communicates with a large array of randomly accessible storage locations, each of which contains one word of a given number of bits. The assembly of these locations, the "random access memory," typically consists of one discrete element for each bit stored, which occupies a fixed location in space. This approach is comparatively costly. At present, the cycle time for such a memory of megabit size is of the order of one microsecond. Since cost and size normally prohibit providing storage for more than a few million bits in this form, additional bulk memory is pro659 660 THE BELL SYSTEM TECHNICAL JOURNAL, MARCH 1969 vided in which bits are stored in homogeneous media at lower cost and higher density. Since the bit locations in this bulk memory are basically defined by sequential scanning from a given addressable starting location, the information has to be stored or read out sequentially as a block. Therefore, once the desired block is addressed, a certain latency time passes until the information is available. This typically ranges from 10 to 100 milliseconds in mechanically scanned systems such as drums or disks and is even longer if heads have to be repositioned. If the information is stored on magnetic tape, this latency time may be several minutes. The present trend is to have shorter processor cycle times and multiple access facilities in evolving computers; increasing emphasis is put on the ability to transfer blocks of information quickly between a bulk store and the random-access memory with which the processor interacts.