Reduction of the Base Collector Capacitance of Heterostructure Bipolar Transistors Using Regrowth Over a Patterned Subcollector

Here we report on the use of regrowth over a patterned subcollector to achieve a reduction in the base-collector capacitance, C sub BC , for InP/InGaAs latticed matched to InP based HBT devices. After patterning the subcollector, an initial MOCVD regrowth is done followed by MOMBE regrowth of the remainder of the structure. All of the lithography was done using a stepper. We have developed a process to protect the initial alignment features during the regrowth steps to ensure proper realignment. This is a critical issue, particularly for the smaller devices where the regrowth technique can have an advantage. Results for devices with a 2x8 microns sup 2 emitter strip gave maximum f sub T and f sub max values of 105 GHz and 130 GH, respectively. These values were limited by a somewhat high collector resistance due to an etching problem near the subcollector which increased the contact resistance. More importantly, C sub BC values of 12.5 fF and 9 fF for a 2x8 microns sup 2 device were extracted from the s-parameter data at I sub c = 2 mA and 9.5 mA, respectively. This seems to indicate that only the area where the initial subcollector was defined contributed to C sub BC. In the layout of the device, the actual base area is > 100 microns sup 2 which would give about 33 fF assuming 0.33 fF/microns sup 2 for a 300 nm collector thickness. The measured values were closer to actual patterned subcollector area of about 300 microns sup 2.