SATYA: A Simulation-Based Test Systems for High-Level Synthesis Verification

We present a new and practical approach to show the correctness of high-level synthesis systems. A high-level synthesis system maps an algorithmic-level behavioral description into a logic-level circuit description. An unique simulation-based approach is used to check the equivalence of the logic-level description and the behavioral description. Using the approach, semantic errors in the BRIDGE high-level synthesis system and in the user-supplied behavioral descriptions have been detected and their causes identified. The BRIDGE synthesis system accepts a powerful subset of the C programming language as input. The problems that occur for verification from using this high-level language would similarly occur for synthesis from other high-level languages such as VHDL. We do not know of any such synthesis verification tools that exists currently.