Selection of a Rate Adaptation Scheme for Network Hardware

Rate adaptation is a family of technologies driven by the expectation that large energy savings can be achieved in packet networks by dynamically adjusting the capacity of network components to the load that they are required to sustain. Depending on the scope of their application, whether at the network, system, or circuit-pack level, specific instances of the rate adaptation concept differ widely by their timescale of operation. In this paper we focus on packet-timescale rate adaptation (PTRA) techniques, which apply to individual traffic processing chips in the circuit packs of network systems. We look at the field of available options for PTRA implementation, whose behavior has been so far well characterized only in single-device applications, and compare their performance in realistic multidevice configurations. We find that the sleep-state-exploitation (SSE) scheme, which only adds a sleep state to the ordinary fullcapacity state, offers the best compromise between energy savings and the packet delay degradation that PTRA unavoidably introduces. We then study the effects of SSE on the utilization of a bottleneck link in the data path of a set of TCP connections. We recognize the need for buffer size adjustments to compensate for the presence of SSE devices along the data path, in measures that largely depend on the buffer management policy that regulates access to the bottleneck queue. The adjustment needed with the recently defined periodic early detection (PED) scheme is considerably smaller than that required by the conventional taildrop policy and almost negligible in configurations of practical relevance.