Self test circuit for embedded RAMs, ROMs, and PLAs in VLSI Devices.

Testing RAMs, ROMs, and PLAs which are embedded in VLSI devices has typically been difficult. This document describes a design approach which provides a built-in self-test of the embedded function. The technique requires a counter which provides the test patterns to the function under test and controls the testing sequence and a linear feedback shift register to compress the output data from the function via signature analysis.