Staggered transpose form equalizer using a RAM (RAM-EQ)

Adaptive filters account for a large part of the power dissipation and area in a modem chip. Hence considerable effort is spent in optimizing the architecture of the adaptive filters. In this paper we propose an architecture which takes into consideration the present state of VLSI technology and the constraints of a practical system. The equalizer uses a staggered transpose form architecture which allows the use of RAMs instead of discrete delay registers. Also, hardware sharing is on inherent characteristic of the architecture. The architecture is fully pipelined and programmable for rear or complex filtering.