Studies of effective gettering techniques using segregation annealing for CMOS VLSI technologies.

Reported in this work are a series of experiments which demonstrate conditions by which metallic impurities may be gettered in a CMOS VLSI technology. Successful gettering is shown to reduce reverse biased pn junction leakage by up to three orders of magnitude. The gettering technique we investigated emphasize segregation annealing whereby impurities diffuse to heavily doped regions of the wafer. In addition, intrinsic gettering by oxygen precipitates and extrinsic gettering through phosphorus diffusion or wafer backside ion implantation, and addition of HCl to furnace oxidation/diffusion steps were studied. It is our conclusion that a combination of these gettering methods offers the greatest reduction in junction leakage. Application to state of the art and future fine line CMOS technologies is indicated by experiments which show that backside implantation of boron or phosphorus followed by segregation annealing allows gettering to proceed at 700-800C, a temperature range consistent with the trend to lower process temperatures. Junction leakage currents were measured indirectly using a hold-time tester structure. The tester allowed routine measurements of current as low as 20 fA. The temperature dependence of the junction leakage is used to calculate activation energies which show that the dominant mechanism of the leakage current changes from generation/recombination to a diffusion component as the hold time increases.