Study of the Quasi-Saturation Effect in VDMOS Transistors

The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behaviour is due to carrier velocity saturation. Two-dimensional numerical simulation is carried out to study the effect of various device parameters on its i-v characteristic in the quasi-saturation mode. Calculated and experimental results at high voltage and current levels are compared and show reasonable agreement. The design constraint on the p-body spacing in order to avoid the quasi-saturation effect is defined.