Submicron salicide CMOS devices with self-aligned shallow/deep junctions - T-MOS.

A triple layer gate spacer (oxide/nitride/Peteos) CMOS (T-MOS) structure has been used to form shallow/deep junctions with deep junction self-aligned to the silicide layer on the source/drain area of submicron CMOS devices. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this unique source/drain junction structure. T-MOS of 0.5micron gate length has been demonstrated with good device characteristics and ideal junction leakage properties.