Superior Metal Step Coverage and Dielectric Quality in a Simple Two-Level Metal 1.0micron CMOS Technology

A two-level metal process for a fourth generation 1.0micron CMOS technology has been developed which yields superior step coverages and void-free dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations, and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and resist-etchback planarization of plasma enhanced TEOS for dielectric II. Also featured are a tapered aluminum I profile and modified contact window and via etch profiles. Defect density and electromigration data predict excellent yield and reliability for this process.