Switched-Capacitor Simulation Models for Full-Chip Verification

This paper describes models and techniques used in a switched-capacitor functional model generator. The proposed method is useful for obtaining functional verification of chips consisting of clock generating circuitry, switched-capacitor circuits and other analog or digital blocks. A program MODGENSC has been developed which generates the models directly from the circuit description in SWITCAP. With this capability, full-chip mixed digital/analog simulation is achievable and also the simulation time is reduced significantly.