System Level Performance Limits and Optical Interconnect Performance (NOT KNOWN IF PUBLISHED BECAUSE AUTHOR HAS LEFT AT&T)

The scaling of silicon VLSI to higher density presents a significant challenge to the system designer, illustrated by the following example. The recently announced Intel i486 32-bit microprocessor integrates on a single chip (with about 10 sup 6 devices) a complete 32-bit minicomputer-performance processor with advanced memory management, data and address cache, a high performance floating point accelerator, etc. The device density will certainly evolve to 10 sup 7 and possibly to 10 sup 8 devices/chip, providing single chip functional complexity of 10-100 high performance processor units. With current DRAMs providing 128 Kbyte/chip, the 10-100 fold scaling of device density will give 1-10 Mbyte/chip. Though impressive capabilities at the chip level, wafer-scale technologies increase the number of processors and the amount of memory per monolithic component by another factor of 100.