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    Systolic Linear Array Processor Rasterized Image Generation (NOT PUBLISHED)

Systolic Linear Array Processor Rasterized Image Generation (NOT PUBLISHED)

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A cellular array device suitable for Wafer Scale Integration is described that converts object descriptions in the form of planar polygonal data into 2-D rasterized graphical images. Fault tolerance is provided by a dynamically switched data path that allows the device to be reconfigured by software and reused in the event of cell failures.