The 3B20D Processor & DMERT Operating System: 3B20D Packaging and Technology

The cost, performance, and schedule objectives of the 3B20D Processor and the overall complexity of the design required: · A full spectrum of circuit integration · Common integrated circuit specifications · A broad range of semiconductor memory devices · A standard hardware packaging technology · Quick turnaround prototype circuit packs · High interconnection capability at the circuit pack level · A hierarchy computer aided design (CAD) process · Comprehensive design audits in the CAD process. The use of Bellpac* packaging system technology provides a dense, high performance packaging system.1 This includes a substantial increase in the number of devices allowed per circuit pack and the number of contacts per pack over previous technologies. The use of Bellpac packaging technology also allowed a low system cost since the * Bellpac is a trademark of Western Electric. 221 hardware is Bell System standard and manufactured in high volume. Complex integrated circuits from a variety of vendors were employed throughout the 3B20D Processor. A wide variety of integrated circuits and comprehensive specifications were used to optimize processor performance, cost, and reliability. Bellpac packaging technology and the integrated circuits were coupled together through a sophisticated CAD system. The CAD system is comprised of design, analysis, simulation, and audit tools at device, circuit pack, unit, and frame levels.