The 3B20D Processor & DMERT Operating System: 3B20D Processor Memory Systems

The memory system associated with the 3B20D Processor 1 includes a 16-megabyte memory, a high-speed cache memory, and hardware assistance for the virtual-to-physical address translation process, access protection, and memory resource arbitration functions. 2 The memory system utilizes high-speed, static and dynamic memory devices and appropriate logic controllers. The block diagram shown in Fig. 1 highlights the major components and interconnections of the 3B20D Memory System. The diagram indicates the memory system related control, address, and data paths, including the interconnection to the fully duplicated system. Internal central control data paths associated with the Store Address Translator (SAT) are not shown. As indicated, the 3B20D Memory System is comprised of a 16207 Fig. 1--Block diagram of the 3B20D Processor memory system.