The 3B20D Processor & DMERT Operating System: Fault Detection and Recovery

The 3B20D Processor has extensive maintenance subsystems associated with it and is designed to meet the high-availability standards of Bell System electronic switching systems. This implies that the processor must perform within an objective of not more than two minutes downtime per service year when used in an electronic switching application. The many subsystems that have been developed to provide the high-availability capability are described in this article. In particular, software and hardware fault recovery are discussed along with the microcode assists for the recovery. Much evolution has taken place in recovery architectures for electronic switching systems. 12 Earlier processor systems used extensive hardware-matching algorithms that resulted in intricate software recovery.''4 More recent hardware technologies have enabled the costeffective design of processor systems with unique fault-detection capabilities.1,5,6 These capabilities have led to much simpler recovery software. This article describes the detection mechanisms for the 3B20D and the software maintenance architecture. 349