The Design of a VLSI Memory Management Unit/Data Cache Chip for the WE(R)32200 Microprocessor Family (NOT PUBLISHED)

The WE 32201 Integrated Memory Management Unit/Data Cache is the first device to include a CAM (Content Addressable Memory) based address translation mechanism, and a Data Cache on a single chip. The chip offers extensive performance and feature enhancements over, but is still operating system and protocol compatible with the WE(R) 32101 MMU [1]. The chip will be processed using AT&T's 1uM Twin-Tub CMOS. It is implemented on a .98 cm. square die, contains over 400K transistor sites and is housed in a 133-pin pin-grid-array package. The chip dissipates less than 1 watt of power at a typical operating frequency of 24 MHz.