The Implementation of Digital Echo Cancellation in CODECs

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single power supply CMOS device implemented in 1.5micron technology using SIGMADELTA modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high, such that only one set of coefficients per national standard is necessary.