The Implications of Damascene Topography for Electroplated Copper Interconnects

The introduction of Cu metallization in advanced 0.18 micron generation integrated circuits (ICs) involves a revolutionary change in process architecture for multilevel interconnects. In contrast to conventional Al interconnects that are defined by a subtractive metal etch of a planar Al film, the geometries of Cu interconnects are defined by trenches and vias etched in the dielectric that are subsequently filled with metal, as shown in the schematic in Fig. 1. This avoids the problem of having to etch Cu. However, a challenge of a different sort arises from the need to fill these high aspect ratio dual damascene structures without voids in the metal. Line-of-sight physical vapor deposition (PVD) techniques such as sputtering that are currently used for depositing planar Al films are inadequate for filling such features. Accumulation of deposit at the upper corners of the trenches leads to pinch off and void formation. Chemical vapor deposition (CVD) has the potential for conformal coverage, but numerous chemical and hardware issues have hampered development of a manufacturable fill process. Thus, to the surprise of many in both the semiconductor and plating industries, electroplating has emerged as the deposition method of choice for damascene Cu interconnects.