The ISM Multiprocessor

ISM is a shared multiprocessor system supporting up to sixteen CRISP processors on a single backplane. Each cpu has a hierarchy of coherent caches to speed local access and reduce backplane bandwidth. The CRISP cpu itself has software maintained virtually addressed caches. The first level of off-chip cache is designed for zero wait state access and is write through. The second level cache is designed to minimize bus loading and uses a simple three state ownership protocol. The name, ISM, is derived from these snooping cache states: Invalid, Shared, and Modified. I will discuss the goals and design tradeoffs in ISM and current hardware status.