The Vertical Replacement-Gate (VRG) Process for Scalable, General-Purpose Complementary Logic

We describe a process for vertical MOSFETs with: (1) precise gate length below 50 nm with current lithography; (2) gate oxide grown on a single-crystal silicon channel; and (3) shallow, self-aligned source/drain extensions. A proposed CMOS process has comparable density to planar CMOS, twice the drive current, and modest parasitics.